NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION

Details for Australian Patent Application No. 2003297043 (hide)

Owner INTEL CORPORATION

Inventors HARELAND, Scott; CHAU, Robert; DOYLE, Brian; DATTA, Suman; JIN, Been-Yih

Pub. Number AU-A-2003297043

PCT Number PCT/US2003/0397

PCT Pub. Number WO2005/010997

Priority 10/607,632 27.06.03 US

Filing date 12 December 2003

Wipo publication date 14 February 2005

International Classifications

H01L 029/786 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 021/336 Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L 029/10 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 029/423 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

Event Publications

6 May 2004 Complete Application Filed

  Priority application(s): 10/607,632 27.06.03 US

24 March 2005 Application Open to Public Inspection

  Published as AU-A-2003297043

16 March 2006 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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