MICROPROCESSOR AND INSTRUCTION EXECUTION ORDER SCHEDULING METHOD

Details for Australian Patent Application No. 2002232196 (hide)

Owner INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventors UEDA, Makoto

Pub. Number AU-A-2002232196

PCT Pub. Number WO2002/069150

Priority 2001-51539 27.02.01 JP

Filing date 14 February 2002

Wipo publication date 12 September 2002

International Classifications

G06F 012/08 Accessing, addressing or allocating within memory systems or architectures - in hierarchically structured memory systems, e.g. virtual memory systems

G06F 009/30 Arrangements for programme control, e.g. control unit - Arrangements for executing machine- instructions, e.g. instruction decode

G06F 009/38 Arrangements for programme control, e.g. control unit - Concurrent instruction execution, e.g. pipeline, look ahead

G06F 009/32 Arrangements for programme control, e.g. control unit - Address formation of the next instruction, e.g. incrementing the instruction counter, jump

G06F 009/34 Arrangements for programme control, e.g. control unit - Addressing or accessing the instruction operand or the result

Event Publications

6 March 2003 Application Open to Public Inspection

  Published as AU-A-2002232196

12 February 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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