Jitter reduction method and apparatus for distributed synchronised clock architecture

Details for Australian Patent Application No. 2010251772 (hide)

Owner Chronologic Pty. Ltd.

Inventors Foster, Peter Graham; Kouznetsov, Alex

Agent Chronologic Pty. Ltd.

Pub. Number AU-A-2010251772

PCT Pub. Number WO2010/132943

Priority 61/179,904 20.05.09 US

Filing date 20 May 2010

Wipo publication date 25 November 2010

International Classifications

G06F 1/12 (2006.01) Details not covered by groups and - Synchronisation of different clock signals

G06F 1/10 (2006.01) Details not covered by groups and - Distribution of clock signals

G06F 13/14 (2006.01) Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units - Handling requests for interconnection or transfer

H04L 7/08 (2006.01) Arrangements for synchronising receiver with transmitter - the synchronisation signals recurring cyclically

Event Publications

1 December 2011 PCT application entered the National Phase

  PCT publication WO2010/132943 Priority application(s): WO2010/132943

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