Firmware socket module for FPGAbased pipeline processing

Details for Australian Patent Application No. 2007208128 (hide)

Owner Washington University Exegy Incorporated

Inventors Chamberlain, Roger D.; White, Jason R.; Henrichs, Michael; Shands, E.F. Berkley; Brodie, Benjamin C.

Agent Pizzeys

Pub. Number AU-A-2007208128

PCT Pub. Number WO2007/087507

Priority 11/339,892 26.01.06 US

Filing date 22 January 2007

Wipo publication date 2 August 2007

International Classifications

G06F 9/38 (2006.01) Arrangements for programme control, e.g. control unit - Concurrent instruction execution, e.g. pipeline, look ahead

G06F 15/78 (2006.01) Digital computers in general

G06F 15/80 (2006.01) Digital computers in general

Event Publications

4 September 2008 PCT application entered the National Phase

  PCT publication WO2007/087507 Priority application(s): WO2007/087507

8 July 2010 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(a). A direction to request examination has been given for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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