Semiconductor device including a front side strained superlattice layer and a back side stress layer and associated methods

Details for Australian Patent Application No. 2006294552 (hide)

Owner MEARS Technologies, Inc.

Inventors Rao, Kalipatnam Vivek

Agent Pizzeys

Pub. Number AU-A-2006294552

PCT Pub. Number WO2007/038656

Priority 11/534,796 25.09.06 US; 60/720,582 26.09.05 US

Filing date 26 September 2006

Wipo publication date 5 April 2007

International Classifications

H01L 29/15 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 29/10 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

Event Publications

8 May 2008 PCT application entered the National Phase

  PCT publication WO2007/038656 Priority application(s): WO2007/038656

15 April 2010 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(a). A direction to request examination has been given for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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