Semiconductor device including a strained superlattice and overlying stress layer and related methods

Details for Australian Patent Application No. 2006270324 (hide)

Owner MEARS Technologies, Inc.

Inventors Kreps, Scott A.; Mears, Robert J.

Agent Pizzeys

Pub. Number AU-A-2006270324

PCT Pub. Number WO2007/011628

Priority 11/457,293 13.07.06 US; 60/699,949 15.07.05 US; 11/457,286 13.07.06 US

Filing date 14 July 2006

Wipo publication date 25 January 2007

International Classifications

H01L 29/15 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 21/336 (2006.01) Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L 21/8234 (2006.01) Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L 29/10 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

Event Publications

21 February 2008 PCT application entered the National Phase

  PCT publication WO2007/011628 Priority application(s): WO2007/011628

11 February 2010 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(a). A direction to request examination has been given for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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