Semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer and associated methods

Details for Australian Patent Application No. 2006265096 (hide)

Owner MEARS Technologies, Inc.

Inventors Rao, Kalipatnam Vivek

Agent Pizzeys

Pub. Number AU-A-2006265096

PCT Pub. Number WO2007/005862

Priority 60/695,588 30.06.05 US

Filing date 30 June 2006

Wipo publication date 11 January 2007

International Classifications

H01L 29/15 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 29/04 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 29/10 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 29/786 (2006.01) Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

Event Publications

21 February 2008 PCT application entered the National Phase

  PCT publication WO2007/005862 Priority application(s): WO2007/005862

14 January 2010 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(a). A direction to request examination has been given for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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