Semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween and associated methods

Details for Australian Patent Application No. 2006262416 (hide)

Owner MEARS Technologies, Inc.

Inventors Rao, Kalipatnam Vivek

Agent Pizzeys

Pub. Number AU-A-2006262416

PCT Pub. Number WO2007/002043

Priority 60/692,101 20.06.05 US

Filing date 20 June 2006

Wipo publication date 4 January 2007

International Classifications

H01L 21/8238 (2006.01) Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L 21/762 (2006.01) Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Event Publications

31 January 2008 PCT application entered the National Phase

  PCT publication WO2007/002043 Priority application(s): WO2007/002043

14 January 2010 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(a). A direction to request examination has been given for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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