Test terminal negation circuit

Details for Australian Patent Application No. 2005201146 (hide)

Owner Sharp Kabushiki Kaisha

Inventors Shuro FUKUHARA

Agent Davies Collison Cave

Pub. Number AU-B-2005201146

Priority 2004-094572 29.03.04 JP

Filing date 17 March 2005

Wipo publication date 13 October 2005

Acceptance publication date 26 July 2007

International Classifications

G01R 31/28 (2006.01) Arrangements for testing electric properties - Testing of electronic circuits, e.g. by signal tracer

G01R 31/317 (2006.01) Arrangements for testing electric properties

G01R 31/3185 (2006.01) Arrangements for testing electric properties

G06F 21/02 (2006.01) Security arrangements for protecting computers or computer systems against unauthorised activity

G06K 19/07 (2006.01) Record carriers for use with machines and with at least a part designed to carry digital markings - with integrated circuit chips

G11C 29/02 (2006.01) Checking stores for correct operation - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Event Publications

7 April 2005 Complete Application Filed

  Priority application(s): 2004-094572 29.03.04 JP

13 October 2005 Application Open to Public Inspection

  Published as AU-B-2005201146

26 July 2007 Application Accepted

  Published as AU-B-2005201146

22 November 2007 Standard Patent Sealed

12 January 2012 Assignment Registered

  Sharp Kabushiki Kaisha The patent has been assigned to Intellectual Properties I Kft.

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