NAND MEMORY ARRAY INCORPORATING CAPACITANCE BOOSTING OF CHANNEL REGIONS IN UNSELECTED MEMORY CELLS AND METHOD FOR OPERATION OF SAME

Details for Australian Patent Application No. 2003300480 (hide)

Owner MATRIX SEMICONDUCTOR, INC.

Inventors CHEN, En-Hsing; WALKER, Andrew J.,; SCHEUERLEIN, Roy E.,; NALLAMOTHU, Sucheta; ILKBAHAR, Alper; FASOLI, Luca G.,

Pub. Number AU-A-2003300480

PCT Number PCT/US2003/0418

PCT Pub. Number WO2004/061861

Priority 10/335,078 31.12.02 US; 10/335,089 31.12.02 US; 10/729,831 05.12.03 US

Filing date 31 December 2003

Wipo publication date 29 July 2004

International Classifications

G11C 016/34 Erasable programmable read-only memories

G11C 016/04 Erasable programmable read-only memories - using variable threshold transistors, e.g. FAMOS

G11C 016/10 Erasable programmable read-only memories

Event Publications

27 May 2004 Complete Application Filed

  Priority application(s): 10/335,078 31.12.02 US; 10/335,089 31.12.02 US; 10/729,831 05.12.03 US

2 September 2004 Application Open to Public Inspection

  Published as AU-A-2003300480

22 September 2005 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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