MULTILAYERED INTEGRATED CIRCUIT WITH EXTRANEOUS CONDUCTIVE TRACES

Details for Australian Patent Application No. 2003284270 (hide)

Owner BAUKUS, James, P. CHOW, Lap-Wai CLARK, William, M., JR. YANG, Paul, Ou

Inventors YANG, Paul, Ou; CLARK, William, M., JR.; CHOW, Lap-Wai; BAUKUS, James, P.

Pub. Number AU-A-2003284270

PCT Number PCT/US2003/0329

PCT Pub. Number WO2004/038800

Priority 10/686,545 14.10.03 US; 60/420,173 21.10.02 US

Filing date 16 October 2003

Wipo publication date 13 May 2004

International Classifications

H01L 023/58 Details of semiconductor or other solid state devices - Structural electrical arrangements for semiconductor devices not otherwise provided for

H01L 023/528 Details of semiconductor or other solid state devices

H01L 023/522 Details of semiconductor or other solid state devices

H01L 027/02 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate - including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier

Event Publications

25 March 2004 Complete Application Filed

  Priority application(s): 10/686,545 14.10.03 US; 60/420,173 21.10.02 US

17 June 2004 Application Open to Public Inspection

  Published as AU-A-2003284270

21 July 2005 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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