TECHNIQUE FOR FABRICATING LOGIC ELEMENTS USING MULTIPLE GATE LAYERS

Details for Australian Patent Application No. 2003281425 (hide)

Owner SANDISK CORPORATION

Inventors MOKHLESI, Nima; LUTZE, Jeffrey

Pub. Number AU-A-2003281425

PCT Number PCT/US2003/0204

PCT Pub. Number WO2004/006338

Priority 10/211,433 02.08.02 US; 60/421,115 02.07.02 US

Filing date 25 June 2003

Wipo publication date 23 January 2004

International Classifications

H01L 029/78 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier

H01L 027/11 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate - Static random access memory structures

Event Publications

4 March 2004 Complete Application Filed

  Priority application(s): 10/211,433 02.08.02 US; 60/421,115 02.07.02 US

11 March 2004 Application Open to Public Inspection

  Published as AU-A-2003281425

21 July 2005 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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