HIERARCHICAL TEST METHODOLOGY FOR MULTI-CORE CHIPS

Details for Australian Patent Application No. 2003249712 (hide)

Owner SUN MICROSYSTEMS, INC.

Inventors PENDURKAR, Rajesh, Y.

Pub. Number AU-A-2003249712

PCT Number PCT/US03/21101

PCT Pub. Number WO2004/005949

Priority 10/189,870 03.07.02 US

Filing date 2 July 2003

Wipo publication date 23 January 2004

International Classifications

G01R 031/3185 Arrangements for testing electric properties

G11C 029/00 Checking stores for correct operation

Event Publications

16 October 2003 Complete Application Filed

  Priority application(s): 10/189,870 03.07.02 US

11 March 2004 Application Open to Public Inspection

  Published as AU-A-2003249712

7 April 2005 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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