METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS

Details for Australian Patent Application No. 2003247794 (hide)

Owner MICRON TECHNOLOGY, INC.

Inventors BATRA, Shubneesh; CHAINE, Michael, D.; KEETH, Brent; AKRAM, Salman; MANNING, Troy, A.; JOHNSON, Brian; MARTIN, Chris, G.; MERRITT, Todd, A.; SMITH, Eric, J.

Pub. Number AU-A-2003247794

PCT Number PCT/US03/21029

PCT Pub. Number WO2004/001846

Priority 10/178,172 21.06.02 US; 10/293,789 12.11.02 US

Filing date 18 June 2003

Wipo publication date 6 January 2004

International Classifications

H01L 023/485 Details of semiconductor or other solid state devices

H01L 023/64 Details of semiconductor or other solid state devices

Event Publications

2 October 2003 Complete Application Filed

  Priority application(s): 10/178,172 21.06.02 US; 10/293,789 12.11.02 US

4 March 2004 Application Open to Public Inspection

  Published as AU-A-2003247794

7 April 2005 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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