USING MULTIPLE STATUS BITS PER CELL FOR HANDLING POWER FAILURES DURING WRITE OPERATIONS

Details for Australian Patent Application No. 2003217254 (hide)

Owner INTEL CORPORATION

Inventors SRINIVASAN, Sujaya

Pub. Number AU-A-2003217254

PCT Number PCT/US03/02373

PCT Pub. Number WO2003/071551

Priority 10/077,428 15.02.02 US

Filing date 24 January 2003

Wipo publication date 9 September 2003

International Classifications

G11C 011/56 Digital stores characterised by the use of particular electric or magnetic storage elements - using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

G11C 016/34 Erasable programmable read-only memories

Event Publications

31 July 2003 Complete Application Filed

  Priority application(s): 10/077,428 15.02.02 US

9 October 2003 Application Open to Public Inspection

  Published as AU-A-2003217254

4 November 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

Legal

The information provided by the Site not in the nature of legal or other professional advice. The information provided by the Site is derived from third parties and may contain errors. You must make your own enquiries and seek independent advice from the relevant industry professionals before acting or relying on any information contained herein. Check the above data against the Australian Patent Office AUSPAT database.

Next and Previous Patents/Applications

2003217255-METHOD AND APPARATUS FOR VARIABLE LENGTH CODING OF BIT PLANES

2003217253-SYSTEM AND METHOD FOR SENSING AND EVALUATING PHYSIOLOGICAL PARAMETERS AND MODELING AN ADAPTABLE PREDICTIVE ANALYSIS FOR SYMPTOMS MANAGEMENT