ARRANGEMENT OF INTEGRATED CIRCUITS IN A MEMORY MODULE

Details for Australian Patent Application No. 2003213767 (hide)

Owner NETLIST, INC.

Inventors BHAKTA, Jayesh, R.; PAULEY, Robert, S., Jr.

Pub. Number AU-A-2003213767

PCT Number PCT/US03/06978

PCT Pub. Number WO2003/077132

Priority 10/094,512 07.03.02 US

Filing date 6 March 2003

Wipo publication date 22 September 2003

International Classifications

G06F 012/00 Accessing, addressing or allocating within memory systems or architectures

G06F 012/16 Accessing, addressing or allocating within memory systems or architectures - Protection against loss of memory contents

G06F 013/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

G06F 013/28 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

H05K 007/00 Constructional details common to different types of electric apparatus

G06F 012/14 Accessing, addressing or allocating within memory systems or architectures - Protection against unauthorised use of memory

Event Publications

31 July 2003 Complete Application Filed

  Priority application(s): 10/094,512 07.03.02 US

30 October 2003 Application Open to Public Inspection

  Published as AU-A-2003213767

25 November 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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