CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS

Details for Australian Patent Application No. 2002352993 (hide)

International Classifications

Event Publications

20 March 2003 Complete Application Filed

Priority application(s): 10/026,103 19.12.01 US

2 October 2003 Application Open to Public Inspection

Published as AU-A-2002352993

2 September 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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