TEST CIRCUIT TOPOLOGY RECONFIGURATION AND UTILIZATION TECHNIQUES

Details for Australian Patent Application No. 2002343162 (hide)

International Classifications

Event Publications

27 February 2003 Complete Application Filed

Priority application(s): 09/997,784 30.11.01 US

21 August 2003 Application Open to Public Inspection

Published as AU-A-2002343162

19 August 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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