METHOD AND ARCHITECTURE FOR SELF-CLOCKING DIGITAL DELAY LOCKED LOOP

Details for Australian Patent Application No. 2002342192 (hide)

Owner CYPRESS SEMICONDUCTOR CORP.

Inventors FISCUS, Timothy, E.

Pub. Number AU-A-2002342192

PCT Number PCT/US02/34665

PCT Pub. Number WO2003/039003

Priority 10/074,737 29.10.01 US

Filing date 29 October 2002

Wipo publication date 12 May 2003

International Classifications

H03L 007/06 Automatic control of frequency or phase - using a reference signal applied to a frequency- or phase-locked loop

Event Publications

27 February 2003 Complete Application Filed

  Priority application(s): 10/074,737 29.10.01 US

10 July 2003 Application Open to Public Inspection

  Published as AU-A-2002342192

15 July 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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