CHIP-JOIN PROCESS TO REDUCE ELONGATION MISMATCH BETWEEN THE ADHERENTS AND SEMICONDUCTOR PACKAGE MADE THEREBY

Details for Australian Patent Application No. 2002340452 (hide)

Owner INTEL CORPORATION

Inventors CHANDRAN, Biju; GONZALEZ, Carlos

Pub. Number AU-A-2002340452

PCT Number PCT/US02/36038

PCT Pub. Number WO2003/059028

Priority 10/023,819 21.12.01 US

Filing date 7 November 2002

Wipo publication date 24 July 2003

International Classifications

H05K 003/30 Apparatus or processes for manufacturing printed circuits - Assembling printed circuits with electric components, e.g. with resistor

H05K 003/34 Apparatus or processes for manufacturing printed circuits - by soldering

Event Publications

27 February 2003 Complete Application Filed

  Priority application(s): 10/023,819 21.12.01 US

4 September 2003 Application Open to Public Inspection

  Published as AU-A-2002340452

9 September 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

Legal

The information provided by the Site not in the nature of legal or other professional advice. The information provided by the Site is derived from third parties and may contain errors. You must make your own enquiries and seek independent advice from the relevant industry professionals before acting or relying on any information contained herein. Check the above data against the Australian Patent Office AUSPAT database.

Next and Previous Patents/Applications

2002340453-DEVICE AND METHOD FOR PACKAGE WARP COMPENSATION IN AN INTEGRATED HEAT SPREADER

2002340451-Human monoclonal antibodies to dendritic cells