AN ENHANCED GENERAL INPUT/ OUTPUT ARCHITECTURE AND RELATED METHODS FOR ESTABLISHING VIRTUAL CHANNELS THEREIN

Details for Australian Patent Application No. 2002331924 (hide)

Owner INTEL CORPORATION

Inventors AJANOVIC, Jasmin; HARRIMAN, David

Pub. Number AU-A-2002331924

PCT Number PCT/US02/31003

PCT Pub. Number WO2003/029995

Priority 09/968,620 30.09.01 US

Filing date 27 September 2002

Wipo publication date 14 April 2003

International Classifications

G06F 013/12 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units - using hardware independent of the central processor, e.g. channel or peripheral processor

Event Publications

6 February 2003 Complete Application Filed

  Priority application(s): 09/968,620 30.09.01 US

26 June 2003 Application Open to Public Inspection

  Published as AU-A-2002331924

17 June 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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