A GENERAL INPUT/OUTPUT ARCHITECTURE PROTOCOL AND RELATED METHODS TO MANAGE DATA INTEGRITY

Details for Australian Patent Application No. 2002326752 (hide)

Owner INTEL CORPORATION (a Delaware Corporation) (a Delawware Corporation)

Inventors WEHAGE, Eric; AJANOVIC, Jasmin; HARRIMAN, David, J.; LEE, David, M.; FANNING, Blaise; GREMEL, Buck; CRETA, Ken; MOORE, Wayne, A.

Pub. Number AU-A-2002326752

PCT Number PCT/US02/27043

PCT Pub. Number WO2003/019391

Priority 60/314,708 24.08.01 US

Filing date 23 August 2002

Wipo publication date 10 March 2003

International Classifications

G06F 013/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Event Publications

23 January 2003 Complete Application Filed

  Priority application(s): 60/314,708 24.08.01 US

5 June 2003 Application Open to Public Inspection

  Published as AU-A-2002326752

10 June 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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