A GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO SUPPORT LEGACY INTERRUPTS

Details for Australian Patent Application No. 2002313815 (hide)

Owner INTEL CORPORATION

Inventors AJANOVIC, Jasmin; HARRIMAN, David, J.; CAMPBELL, Randolph, L.; VARGAS, Jose, A.; HALL, Clifford; SETHI, Prashant; PAWLOWSKI, Steve

Pub. Number AU-A-2002313815

PCT Number PCT/US02/27042

PCT Pub. Number WO2003/019394

Priority 60/314,708 24.08.01 US

Filing date 23 August 2002

Wipo publication date 10 March 2003

International Classifications

G06F 013/12 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units - using hardware independent of the central processor, e.g. channel or peripheral processor

G06F 013/24 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Event Publications

2 January 2003 Complete Application Filed

  Priority application(s): 60/314,708 24.08.01 US

5 June 2003 Application Open to Public Inspection

  Published as AU-A-2002313815

10 June 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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