METHOD AND SYSTEM FOR PREDICTIVE MOSFET LAYOUT GENERATION WITH REDUCED DESIGN CYCLE

Details for Australian Patent Application No. 2002310018 (hide)

Owner CONEXANT SYSTEMS, INC.

Inventors LAMPAERT, Koen; BROTMAN, Andy; MILIOZZI, Paolo; SINGH, Paramjit; MATLOUBIAN, Mishel; BHATTACHARYYA, Bijan

Pub. Number AU-A-2002310018

PCT Number PCT/US02/16124

PCT Pub. Number WO2002/101599

Priority 09/879,142 12.06.01 US

Filing date 21 May 2002

Wipo publication date 23 December 2002

International Classifications

G06F 017/50 Digital computing or data processing equipment or methods, specially adapted for specific functions - Computer-aided design

Event Publications

19 December 2002 Complete Application Filed

  Priority application(s): 09/879,142 12.06.01 US

15 May 2003 Application Open to Public Inspection

  Published as AU-A-2002310018

11 March 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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