METHOD AND SYSTEM TO OPTIMIZE TEST COST AND DISABLE DEFECTS FOR SCAN AND BIST MEMORIES

Details for Australian Patent Application No. 2002257073 (hide)

Owner SYNTEST TECHNOLOGIES, INC.

Inventors VU, Anthony, M.; PARK, Yo, Han; WANG, Laung-Terng (L.-T.); LIN, ShyhHorng; WANG, Hsin-Po; WEN, Xiaoqing; HSU, Chi-Chan

Pub. Number AU-A-2002257073

PCT Pub. Number WO2002/084668

Priority 60/282,917 10.04.01 US; 10/116,128 05.04.02 US

Filing date 9 April 2002

Wipo publication date 28 October 2002

International Classifications

G11C 007/00 Arrangements for writing information into, or reading information out from, a digital store

G11C 029/00 Checking stores for correct operation

G01R 031/28 Arrangements for testing electric properties - Testing of electronic circuits, e.g. by signal tracer

Event Publications

17 April 2003 Application Open to Public Inspection

  Published as AU-A-2002257073

19 February 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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