MONOTONIC DYNAMIC-STATIC PSEUDO-NMOS LOGIC CIRCUIT AND METHOD OF FORMING A LOGIC GATE ARRAY

Details for Australian Patent Application No. 2002238056 (hide)

Owner MICRON TECHNOLOGY, INC.

Inventors FORBES, Leonard

Pub. Number AU-A-2002238056

PCT Pub. Number WO2002/071611

Priority 09/788,109 15.02.01 US

Filing date 7 February 2002

Wipo publication date 19 September 2002

International Classifications

H03K 019/00 Logic circuits, i.e. having at least two inputs acting on one output

Event Publications

13 March 2003 Application Open to Public Inspection

  Published as AU-A-2002238056

12 February 2004 Application Lapsed, Refused Or Withdrawn, Patent Ceased or Expired

  This application lapsed under section 142(2)(f)/See Reg. 8.3(3). Examination has not yet been requested or directed for this application. Note that applications or patents shown as lapsed or ceased may be restored at a later date.

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